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integrated circuit systems, inc. ICS950223 0496c?05/06/05 block diagram pin configuration recommended application: brookdale and brookdale-g chipset with p4 processor. output features: 3 - pairs of differential cpu clocks (differential current mode) 3 - 3v66 @ 3.3v 10 - pci @ 3.3v 1 - 48mhz @ 3.3v fixed 2 - ref @ 3.3v, 14.318mhz 1 - 48_66mhz selectable @ 3.3v fixed 1 - 24_48mhz selectable @ 3.3v features/benefits: quadrom tm frequency selection. programmable output frequency. programmable asynchronous 3v66 & pci frequency. programmable output divider ratios. programmable output rise/fall time. programmable output skew. programmable spread percentage for emi control. watchdog timer technology to reset system if system malfunctions. programmable watchdog safe frequency. support i 2 c index read/write and block read/write operations. uses external 14.318mhz reference input. key specifications: ? cpu output jitter <150ps 3v66 output jitter <250ps cpu output skew <100ps programmable timing control hub? for p 4 ? frequency table pll2 pll1 spread spectrum 48mhz pciclk (9:0) 3v66 (2:0) 24_48mhz x1 x2 xtal osc cpu divder pci divder 3v66 divder pd# multsel(1:0) s data sclk vtt_pwrgd# sel 48_24# sel 66_48# fs (4:0) i ref reset# control logic config. reg. ref (1:0) 3 10 4 3 cpuclkt (2:0) cpuclkc (2:0) / 2 3v66 divder 3v66_48mhz *multsel1/ref1 1 48 ref0/multsel0** vddref 2 47 gndref x1 3 46 vddcpu x2 4 45 cpuclkt2 gnd 5 44 cpuclkc2 *fs2/pciclk0 6 43 gndcpu *fs3/pciclk1 7 42 pd#* **sel48_24#/pciclk2 8 41 cpuclkt0 vddpci 9 40 cpuclkc0 *fs4/pciclk3 10 39 vddcpu pc ic lk4 11 38 cpuclkt1 pc ic lk5 12 37 cpuclkc1 gnd 13 36 gndcpu pc ic lk6 14 35 iref pc ic lk7 15 34 avdd pc ic lk8 16 33 gnd pc ic lk9 17 32 vdd3v66 vddpci 18 31 3v66_0 vttpwr_gd# 19 30 3v66_1 reset# 20 29 gnd gnd 21 28 3v66_2 ~ *fs0/48mhz 22 27 3v66_3_48mhz/sel66_48#** *fs1/24_48mhz 23 26 sclk avdd4824 25sdata 48-ssop * internal pull-up resistor ** internal pull-down resistor ICS950223 ~ this output has 2x drive strength bit4 bit3 bit2 bit1 bit0 cpu 3v66 pci fs4fs3fs2fs1fs0 mhz mhz mhz 00000 102.00 68.00 34.00 00001 105.00 70.00 35.00 00010 108.00 72.00 36.00 00011 111.00 74.00 37.00 00100 114.00 76.00 38.00 00101 117.00 78.00 39.00 00110 120.00 80.00 40.00 00111 123.00 82.00 41.00 01000 126.00 72.00 36.00 01001 130.00 74.29 37.14 01010 136.00 68.00 34.00 01011 140.00 70.00 35.00 01100 144.00 72.00 36.00 01101 148.00 74.00 37.00 01110 152.00 76.00 38.00 01111 156.00 78.00 39.00 10000 160.00 80.00 40.00 10001 164.00 82.00 41.00 10010 166.60 66.64 33.32 10011 170.00 68.00 34.00 10100 175.00 70.00 35.00 10101 180.00 72.00 36.00 10110 185.00 74.00 37.00 10111 190.00 76.00 38.00 11000 66.80 66.80 33.40 11001 100.20 66.80 33.40 11010 133.60 66.80 33.40 11011 200.40 66.80 33.40 11100 66.67 66.67 33.34 11101 100.00 66.67 33.33 11110 200.00 66.67 33.33 11111 133.33 66.67 33.33
2 integrated circuit systems, inc. ICS950223 0496c?05/06/05 pin description the ICS950223 is a single chip clock solution for desktop designs using the intel brookdale chipset with pc133 or ddr memory. it provides all necessary clock signals for such a system. the ICS950223 is part of a whole new line of ics clock generators and buffers called tch? (timing control hub). ics is the first to introduce a whole product line which offers full programmability and flexibility on a single clock device. this part incorpo rates ics's newest clock technology which offers more robust features and functionality. employing the use of a serially programmable i 2 c interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. tch also incorpor ates ics's watchdog timer technology and a reset feature to provide a safe setting under unstable system conditions. m/n control can configure output frequency with resolution up to 0.1mhz increment. with all these programmable features ics's, tch makes mother board testing, tuning and improvement very simple. general description pin pin pin # name type 1 *multsel1/ref1 i/o 3.3v lvttl input for selection the current multiplier for cpu outputs / 14.318 mhz reference clock. 2 vddref pwr ref, xtal power supply, nominal 3.3v 3 x1 in cr y stal in p ut, nominall y 14.318mhz. 4 x2 out cr y stal out p ut, nominall y 14.318mhz 5 gnd pwr ground p in. 6 *fs2/pciclk0 i/o fre q uenc y select latch in p ut p in / 3.3v pci clock out p ut. 7 *fs3/pciclk1 i/o fre q uenc y select latch in p ut p in / 3.3v pci clock out p ut. 8 **sel48_24#/pciclk2 i/o latched select input for 48/24mhz output. 0=24mhz, 1 = 48mhz / 3.3v pci clock output. 9 v ddpci pwr power su pp l y for pci clocks, nominal 3.3v 10 *fs4/pciclk3 i/o fre q uenc y select latch in p ut p in / 3.3v pci clock out p ut. 11 pciclk4 out pci clock out p ut. 12 pciclk5 out pci clock out p ut. 13 gnd pwr ground p in. 14 pciclk6 out pci clock out p ut. 15 pciclk7 out pci clock out p ut. 16 pciclk8 out pci clock out p ut. 17 pciclk9 out pci clock out p ut. 18 v ddpci pwr power su pp l y for pci clocks, nominal 3.3v 19 vttpwr_gd# in this 3.3v lvttl input is a level sensitive strobe used to determine when latch inputs are valid and are read y to be sam p led. this is an active low in p ut. 20 reset# out real time system reset signal for frequency gear ratio change or watchdog timer timeout. this si g nal is active low. 21 gnd pwr ground p in. 22 ~*fs0/48mhz i/o fre q uenc y select latch in p ut p in / fixed 48mhz clock out p ut. 3.3v 23 *fs1/24_48mhz i/o fre q uenc y select latch in p ut p in / fixed 24 or 48mhz clock out p ut. 3.3v. 24 a vdd48 pwr power for 24/48mhz outputs and fixed pll core, nominal 3.3v * internal pull-up resistor ** internal pull-down resistor description ~ this output has 2x drive
3 integrated circuit systems, inc. ICS950223 0496c?05/06/05 pin description (continued) pin pin pin # name type 25 sdata i/o data pin for i2c circuitry 5v tolerant 26 sclk in clock pin of i2c circuitry 5v tolerant 27 3v66_3_48mhz/sel66_48#** i/o selectable 66.66mhz, 48mhz clock output / select input for 66.66/48mhz output. 0=48mhz, 1 = 66.66mhz 28 3v66_2 out 3.3v 66.66mhz clock output 29 gnd pwr ground pin. 30 3v66_1 out 3.3v 66.66mhz clock output 31 3v66_0 out 3.3v 66.66mhz clock output 32 vdd3v66 pwr power pin for the 3v66 clocks. 33 gnd pwr ground pin. 34 avdd pwr 3.3v analog power pin for core pll 35 iref out this pin establishes the reference current for the differential current-mode output pairs. this pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 36 gndcpu pwr ground pin for the cpu outputs 37 cpuclkc1 out "complimentary" clocks of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 38 cpuclkt1 out "true" clocks of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 39 vddcpu pwr supply for cpu clocks, 3.3v nominal 40 cpuclkc0 out "complimentary" clocks of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 41 cpuclkt0 out "true" clocks of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 42 pd#* in asynchronous active low input pin used to power down the device into a low power state. the internal clocks are disabled and the vco and the crystal are stopped. the latency of the power down will not be greater than 1.8ms. 43 gndcpu pwr ground pin for the cpu outputs 44 cpuclkc2 out "complimentary" clocks of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 45 cpuclkt2 out "true" clocks of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 46 vddcpu pwr supply for cpu clocks, 3.3v nominal 47 gndref pwr ground pin for the ref outputs. 48 ref0/multsel0** i/o 3.3v lvttl input for selection the current multiplier for cpu outputs / 14.318 mhz reference clock. * internal pull-up resistor ** internal pull-down resistor description ~ this output has 2x drive
4 integrated circuit systems, inc. ICS950223 0496c?05/06/05 maximum allowed current n o i t i d n o c n o i t p m u s n o c y l p p u s v 3 . 3 x a m , s d a o l p a c e t e r c s i d x a m v 5 6 4 . 3 = d d v d n g r o d d v = s t u p n i c i t a t s l l a e d o m n w o d r e w o p ) 0 = # n w d r w p ( a m 0 4 e v i t c a l l u f a m 0 6 3 0 l e s t l u m1 l e s t l u m t e g r a t d r a o b z m r e t / e c a r t , r e c n e r e f e r = f e r i ) r r * 3 ( / d d v t u p t u o t n e r r u c , z @ h o v a m 2 3 . 2 = f e r i 00 s m h o 0 6 % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 5 = h o i0 6 @ v 1 7 . 0 00 s m h o 0 5 % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 5 = h o i0 5 @ v 9 5 . 0 01 s m h o 0 6 % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 6 = h o i0 6 2 / v 5 8 . 0 01 s m h o 0 5 % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 6 = h o i0 5 @ v 1 7 . 0 10 s m h o 0 6 % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 4 = h o i0 6 @ v 6 5 . 0 10 s m h o 0 5 % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 4 = h o i0 5 @ v 7 4 . 0 11 s m h o 0 6 % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 7 = h o i0 6 @ v 9 9 . 0 11 s m h o 0 5 % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 7 = h o i0 5 @ v 2 8 . 0 00 ) v i u q e c d ( 0 3 % 1 1 2 2 = r r a m 5 = f e r i f e r i * 5 = h o i0 3 @ v 5 7 . 0 00 ) v i u q e c d ( 5 2 % 1 1 2 2 = r r a m 5 = f e r i f e r i * 5 = h o i0 2 @ v 2 6 . 0 01 ) v i u q e c d ( 0 3 % 1 1 2 2 = r r a m 5 = f e r i f e r i * 6 = h o i0 3 @ v 0 9 . 0 01 ) v i u q e c d ( 5 2 % 1 1 2 2 = r r a m 5 = f e r i f e r i * 6 = h o i0 2 @ v 5 7 . 0 10 ) v i u q e c d ( 0 3 % 1 1 2 2 = r r a m 5 = f e r i f e r i * 4 = h o i0 2 @ 0 6 . 0 10 ) v i u q e c d ( 5 2 % 1 1 2 2 = r r a m 5 = f e r i f e r i * 4 = h o i0 2 @ v 5 . 0 11 ) v i u q e c d ( 0 3 % 1 1 2 2 = r r a m 5 = f e r i f e r i * 7 = h o i0 3 @ v 5 0 . 1 11 ) v i u q e c d ( 5 2 % 1 1 2 2 = r r a m 5 = f e r i f e r i * 7 = h o i0 2 @ v 4 8 . 0 cpuclk swing select functions
5 integrated circuit systems, inc. ICS950223 0496c?05/06/05 general i 2 c serial interface information how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 (see note 2) ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controllor (host) will send a not acknowledge bit controller (host) will send a stop bit *see notes on the following page . ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n a c k a c k data byte count = x a c k ics (slave/receiver) controller (host) x byte a ck a ck
6 integrated circuit systems, inc. ICS950223 0496c?05/06/05 table1: quadrom frequency selection table bit6 bit5 bit4 bit3 bit2 bit1 bit0 cpu 3v66 pci spreading x x fs4 fs3 fs2 fs1 fs0 mhz mhz mhz 0 0 0 0 0 0 0 102.00 68.00 34.00 spread off 0 0 0 0 0 0 1 105.00 70.00 35.00 spread off 0 0 0 0 0 1 0 108.00 72.00 36.00 spread off 0 0 0 0 0 1 1 111.00 74.00 37.00 spread off 0 0 0 0 1 0 0 114.00 76.00 38.00 spread off 0 0 0 0 1 0 1 117.00 78.00 39.00 spread off 0 0 0 0 1 1 0 120.00 80.00 40.00 spread off 0 0 0 0 1 1 1 123.00 82.00 41.00 spread off 0 0 0 1 0 0 0 126.00 72.00 36.00 spread off 0 0 0 1 0 0 1 130.00 74.29 37.14 spread off 0 0 0 1 0 1 0 136.00 68.00 34.00 spread off 0 0 0 1 0 1 1 140.00 70.00 35.00 spread off 0 0 0 1 1 0 0 144.00 72.00 36.00 spread off 0 0 0 1 1 0 1 100.99 67.32 33.66 center spread 0 0 0 1 1 1 0 134.66 67.32 33.66 center spread 0 0 0 1 1 1 1 133.99 67.00 35.00 center spread 0 0 1 0 0 0 0 160.00 80.00 40.00 spread off 0 0 1 0 0 0 1 164.00 82.00 41.00 spread off 0010010 166.60 66.64 33.32 center spread 0 0 1 0 0 1 1 170.00 68.00 34.00 spread off 0 0 1 0 1 0 0 175.00 70.00 35.00 spread off 0 0 1 0 1 0 1 180.00 72.00 36.00 spread off 0 0 1 0 1 1 0 185.00 74.00 37.00 spread off 0 0 1 0 1 1 1 190.00 76.00 38.00 spread off 0 0 1 1 0 0 0 66.80 66.80 33.40 center spread 0 0 1 1 0 0 1 100.20 66.80 33.40 center spread 0 0 1 1 0 1 0 200.40 66.80 33.40 center spread 0 0 1 1 0 1 1 133.60 66.80 33.40 center spread 0 0 1 1 1 0 0 66.67 66.67 33.34 down spread 0 0 1 1 1 0 1 100.00 66.67 33.33 down spread 0 0 1 1 1 1 0 200.00 66.67 33.33 down spread 0011111 133.33 66.67 33.33 down spread
7 integrated circuit systems, inc. ICS950223 0496c?05/06/05 table1: quadrom frequency selection table continued bit6 bit5 bit4 bit3 bit2 bit1 bit0 cpu 3v66 pci x x fs4 fs3 fs2 fs1 fs0 mhz mhz mhz 0100000 114.00 76.00 38.00 0100001 115.00 76.67 38.33 0100010 116.00 77.33 38.67 0100011 117.00 78.00 39.00 0100100 118.00 78.67 39.33 0100101 119.00 79.33 39.67 0100110 120.00 80.00 40.00 0100111 121.00 80.67 40.33 0101000 122.00 81.33 40.67 0101001 123.00 82.00 41.00 0101010 125.00 83.33 41.67 0101011 127.00 84.67 42.33 0101100 129.00 86.00 43.00 0101101 131.00 87.33 43.67 0101110 133.00 88.67 44.33 0101111 135.00 90.00 45.00 0110000 152.00 76.00 38.00 0110001 153.00 76.50 38.25 0110010 154.00 77.00 38.50 0110011 155.00 77.50 38.75 0110100 156.00 78.00 39.00 0110101 157.00 78.50 39.25 0110110 158.00 79.00 39.50 0110111 159.00 79.50 39.75 0111000 160.00 80.00 40.00 0111001 161.00 80.50 40.25 0111010 162.00 81.00 40.50 0111011 163.00 81.50 40.75 0111100 164.00 82.00 41.00 0111101 165.00 82.50 41.25 0 1 1 1 1 1 0 144.00 72.00 36.00 0 1 1 1 1 1 1 148.00 74.00 37.00
8 integrated circuit systems, inc. ICS950223 0496c?05/06/05 table1: quadrom frequency selection table continued bit6 bit5 bit4 bit3 bit2 bit1 bit0 cpu 3v66 pci x x fs4 fs3 fs2 fs1 fs0 mhz mhz mhz 1000000 66.67 66.67 33.34 1000001 68.00 68.00 34.00 1000010 70.00 70.00 35.00 1000011 72.00 72.00 36.00 1000100 74.00 74.00 37.00 1000101 76.00 76.00 38.00 1000110 78.00 78.00 39.00 1000111 80.00 80.00 40.00 1001000 82.00 82.00 41.00 1001001 84.00 84.00 42.00 1001010 86.00 86.00 43.00 1001011 88.00 88.00 44.00 1001100 90.00 90.00 45.00 1001101 92.00 92.00 46.00 1001110 94.00 94.00 47.00 1001111 96.00 96.00 48.00 1010000 98.00 98.00 49.00 1010001 100.00 100.00 50.00 1010010 102.00 102.00 51.00 1010011 104.00 104.00 52.00 1010100 106.00 106.00 53.00 1010101 108.00 108.00 54.00 1010110 110.00 110.00 55.00 1010111 112.00 112.00 56.00 1011000 166.67 66.67 33.33 1011001 167.00 66.80 33.40 1011010 168.00 67.20 33.60 1011011 169.00 67.60 33.80 1011100 170.00 68.00 34.00 1011101 171.00 68.40 34.20 1011110 172.00 68.80 34.40 1011111 173.00 69.20 34.60
9 integrated circuit systems, inc. ICS950223 0496c?05/06/05 table1: quadrom frequency selection table continued bit6 bit5 bit4 bit3 bit2 bit1 bit0 cpu 3v66 pci x x fs4 fs3 fs2 fs1 fs0 mhz mhz mhz 1100000 174.00 69.60 34.80 1100001 175.00 70.00 35.00 1100010 176.00 70.40 35.20 1100011 177.00 70.80 35.40 1100100 178.00 71.20 35.60 1100101 179.00 71.60 35.80 1100110 180.00 72.00 36.00 1100111 181.00 72.40 36.20 1101000 160.00 53.33 26.67 1101001 165.00 55.00 27.50 1101010 170.00 56.67 28.33 1101011 175.00 58.33 29.17 1101100 180.00 60.00 30.00 1101101 185.00 61.67 30.83 1101110 190.00 63.33 31.67 1101111 195.00 65.00 32.50 1110000 200.00 66.67 33.33 1110001 201.00 67.00 33.50 1110010 202.00 67.33 33.67 1110011 203.00 67.67 33.83 1110100 204.00 68.00 34.00 1110101 206.00 68.67 34.33 1110110 208.00 69.33 34.67 1110111 210.00 70.00 35.00 1111000 212.00 70.67 35.33 1111001 214.00 71.33 35.67 1111010 216.00 72.00 36.00 1111011 218.00 72.67 36.33 1111100 220.00 73.33 36.67 1111101 222.00 74.00 37.00 1111110 224.00 74.67 37.33 1111111 226.00 75.33 37.67
10 integrated circuit systems, inc. ICS950223 0496c?05/06/05 i 2 c table: frequency select register bit 7 fs source frequency h/w iic select rw latch inputs iic 0 bit 6 fs6 freq select bit 6 rw 0 bit 5 fs5 freq select bit 5 rw 0 bit 4 fs4 freq select bit 4 rw 0 bit 3 fs3 freq select bit 3 rw 0 bit 2 fs2 freq select bit 2 rw 0 bit 1 fs1 freq select bit 1 rw 0 bit 0 fs0 freq select bit 0 rw 0 i 2 c table: spreading and device behavior control register bit 7 ss1 spread select 1 rw 0 bit 6 ss0 spread select 0 rw 0 bit 4 wds_status wd soft alarm status rw normal alarm 0 bit 3 reserved reserved rw - - 1 bit 2 cput2/cpuc2 output control rw disable enable 1 bit 1 cput1/cpuc1 output control rw disable enable 1 bit 0 cput0/cpuc0 output control rw disable enable 1 ss_en spread enable control rw off control function type 0 1 1pwd 0 see table 1: quadrom frequency selection table pwd see table 2: spread spectrum table on 1 name type - byte 0 - - - pin # control function - - - name - - 45/44 - - byte 1 pin # bit 5 - 38/37 41/40 table2: spread spectrum select ss1 ss0 (byte 1 bit 7) (byte 1 bit 6) 0 0 0.35% spread 1 0 1 0.50% spread 2 1 0 0.75% spread 3 1 1 1.00% spread 4 s p read % note i 2 c table: output control register bit 7 aen# 3v66/pci freq source select rw cpu_pll sy nc fix_pll async 0 bit 6 pciclk9 output control rw disable enable 1 bit 5 pciclk8 output control rw disable enable 1 bit 4 pciclk7 output control rw disable enable 1 bit 3 pciclk6 output control rw disable enable 1 bit 2 pciclk5 output control rw disable enable 1 bit 1 pciclk4 output control rw disable enable 1 bit 0 pciclk3 output control rw disable enable 1 1pwd 12 11 name control function type 0 17 16 - byte 2 pin # 15 14 10
11 integrated circuit systems, inc. ICS950223 0496c?05/06/05 i 2 c table: output control register bit 7 24_48mhz output control rw disable enable 1 bit 6 48mhz output control rw disable enable 1 bit 5 gr_en geashift reset enable rw on off 0 bit 4 24_48 fs source 24_48 frequency h/w / iic select rw latch inputs iic 0 bit 3 fs 24_48 sel24_48 rw 24mhz 48mhz 0 bit 2 pciclk2 output control rw disable enable 1 bit 1 pciclk1 output control rw disable enable 1 bit 0 pciclk0 output control rw disable enable 1 i 2 c table: output control register bit 7 66_48 fs source 66_48 frequency h/w / iic select rw latch inputs iic 0 bit 6 fs 66_48# sel66_48# rw 48mhz 66.66mhz 0 bit 5 3v66_0 output control rw disable enable 1 bit 4 3v66_1 output control rw disable enable 1 bit 3 ref0 output control rw disable enable 1 bit 2 ref1 output control rw disable enable 1 bit 1 3v66_3 output control rw disable enable 1 bit 0 3v66_2 output control rw disable enable 1 i 2 c table: 3v66 & pciclk asynchronous frequency control register bit 7 n pll2 div0 rw - - x bit 6 n pll2 div1 rw - - x bit 5 n pll2 div2 rw - - x bit 4 n pll2 div3 rw - - x bit 3 n pll2 div4 rw - - x bit 2 n pll2 div5 rw - - x bit 1 n pll2 div6 rw - - x bit 0 n pll2 div7 rw - - x i 2 c table: read back register bit 7 wdhrb wd hard alarm status read back r- -x bit 6 sel48_24rb sel48_24# read back r - - x bit 5 sel66_48rb sel66_48# read back r - x bit 4 fs4rb fs4 read back r - - x bit 3 fs3rb fs3 read back r - - x bit 2 fs2rb fs2 read back r - - x bit 1 fs1rb fs1 read back r - - x bit 0 fs0rb fs0 read back r - - x pwd the decimal representation of n pll2 div (0:7) + 8 is equal to vco divider value for pll2. - - - name control function type 0 - 8 7 6 byte 4 pin # type 0 1 pwd control function control function type 0 1 01 pwd 1 pwd 23 control function byte 3 pin # name 22 - - - name - - 31 30 48 1 27 28 - byte 5 pin # - - - byte 6 pin # name type - - - - - - - -
12 integrated circuit systems, inc. ICS950223 0496c?05/06/05 i 2 c table: vendor & revision id register bit 7 rid3 r - - 1 bit 6 rid2 r - - 1 bit 5 rid1 r - - 0 bit 4 rid0 r - - 1 bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 i 2 c table: byte count register bit 7 bc7 rw - - 0 bit 6 bc6 rw - - 0 bit 5 bc5 rw - - 0 bit 4 bc4 rw - - 0 bit 3 bc3 rw - - 1 bit 2 bc2 rw - - 1 bit 1 bc1 rw - - 1 bit 0 bc0 rw - - 1 i 2 c table: watchdog timer register pin # name control function type 0 1 pwd bit 7 wd7 rw - - 0 bit 6 wd6 rw - - 0 bit 5 wd5 rw - - 0 bit 4 wd4 rw - - 0 bit 3 wd3 rw - - 1 bit 2 wd2 rw - - 0 bit 1 wd1 rw - - 0 bit 0 wd0 rw - - 0 i 2 c table: vco control select bit & wd timer control register bit 6 wden watchdog enable rw disable enable 0 bit 4 wd sf4 rw - - 1 bit 3 wd sf3 rw - - 1 bit 2 wd sf2 rw - - 0 bit 1 wd sf1 rw - - 0 bit 0 wd sf0 rw - - 1 0 bit 5 - wdfsen wd safe frequency mode rw latched fs/byte0 wd b10 b(4:0) these bits represent x*290ms the watchdo g timer will wait before it goes to alarm mode. default is 8 x 290ms =2.32 seconds - - - - - pwd writing to this register will configure how man y b y tes will be r ead back, default is 0f = 15 bytes. - - - - - - - - 01pwd byte 8 pin # name control function type 0 1 iic prog. b(11:17) m/n programming enable rw type 0 1 type - byte 7 pin # name control function revision id - - - - vendor id - - - byte 9 - - - pwd bit 7 -m/nen 0 latched input byte 10 pin # name control function - - - writing to these bit will configure the safe frequenc y as b y te 0 bit (6:0) - - -
13 integrated circuit systems, inc. ICS950223 0496c?05/06/05 i 2 c table: vco frequency control register bit 7 n div8 n divider bit 8 rw - - x bit 6 m div6 rw - - x bit 5 m div5 rw - - x bit 4 m div4 rw - - x bit 3 m div3 rw - - x bit 2 m div2 rw - - x bit 1 m div1 rw - - x bit 0 m div0 rw - - x i 2 c table: vco frequency control register bit 7 n div7 rw - - x bit 6 n div6 rw - - x bit 5 n div5 rw - - x bit 4 n div4 rw - - x bit 3 n div3 rw - - x bit 2 n div2 rw - - x bit 1 n div1 rw - - x bit 0 n div0 rw - - x i 2 c table: spread spectrum control register bit 7 ssp7 rw - - x bit 6 ssp6 rw - - x bit 5 ssp5 rw - - x bit 4 ssp4 rw - - x bit 3 ssp3 rw - - x bit 2 ssp2 rw - - x bit 1 ssp1 rw - - x bit 0 ssp0 rw - - x i 2 c table: spread spectrum control register bit 7 reserved reserved r - - 1 bit 6 reserved reserved r - - 0 bit 5 ssp13 rw - - x bit 4 ssp12 rw - - x bit 3 ssp11 rw - - x bit 2 ssp10 rw - - x bit 1 ssp9 rw - - x bit 0 ssp8 rw - - x 1pwd it is recommended to use ics spread % table for spread programming. - - - - type - - - 0 byte 14 pin # name control function - - - - name control function 1 1 0 - - - these spread spectrum bits will program the spread pecentage. it is recommended to use ics spread % table for spread programming. pwd the decimal representation of n div (8:0) + 8 is equal to vco divider value. default at power up = latch-in or byte 0 rom table. type 0 pwd - - - - byte 13 pin # type 0 - - name control function byte 11 pin # - - - 1pwd the decimal representation of m div (6:0) +2 is equal to reference divider value. default at power up = latch-in or byte 0 rom table. - - - - name control function type - - - byte 12 pin # - -
14 integrated circuit systems, inc. ICS950223 0496c?05/06/05 i 2 c table: output divider control register bit 7 cpu div3 rw x bit 6 cpu div2 rw x bit 5 cpu div1 rw x bit 4 cpu div0 rw x bit 3 cpu div3 rw x bit 2 cpu div2 rw x bit 1 cpu div1 rw x bit 0 cpu div0 rw x cpuclk [1:0] divider ratio can be configured via these 4 bits individually. see table 3: divider ratio combination table - - - - type 0 1 pwd cpuclk2 divider ratio can be configured via these 4 bits individually. byte 15 pin # name control function see table 3: divider ratio combination table table 3: cpu, agp and pci divider ratio combination table bit00011011msb 1248 00 0 2 100 4 1000 8 1100 16 01 1 3 101 6 1001 12 1101 24 10 10 5 110 10 1010 20 1110 40 11 11 7 111 14 1011 28 1111 56 lsb address div address div address div address div divider (3:2) divider (1:0) i 2 c table: output divider control register bit 7 3v66 div3 rw x bit 6 3v66 div2 rw x bit 5 3v66 div1 rw x bit 4 3v66 div0 rw x bit 3 3v66 div3 rw x bit 2 3v66 div2 rw x bit 1 3v66 div1 rw x bit 0 3v66 div0 rw x i 2 c table: output divider control register bit 7 3v66inv 3v66[3:2] phase invert rw default inverse x bit 6 3v66inv 3v66[1:0] phase invert rw default inverse x bit 5 cpuinv cpu phase invert rw default inverse x bit 4 cpuinv cpu phase invert rw default inverse x bit 3 pci div3 rw x bit 2 pci div2 rw x bit 1 pci div1 rw x bit 0 pci div0 rw x pwd - pci divider ratio can be configured via these 4 bits individually. see table 3: divider ratio combination table - - - name control function type 0 - 3v66 [1:0] divider ratio can be configured via these 4 bits individually. see table 3: divider ratio combination table - - - 1 type 0 1 pwd byte 16 pin # name control function - 3v66 [3:2] divider ratio can be configured via these 4 bits individually see table 3: divider ratio combination table - - - - byte 17 pin # - - -
15 integrated circuit systems, inc. ICS950223 0496c?05/06/05 table 4: 4-steps skew p rogramming table 4 step 0 1 lsb 0 0ps 250ps - 1 500ps 750ps - msb --- i 2 c table: group skew control register and frequency select pll3 bit 7 cpuskw1 rw 1 bit 6 cpuskw0 rw 0 bit 5 reserved reserved rw - - 0 bit 4 reserved reserved rw - - 0 bit 3 cpuskw1 rw 1 bit 2 cpuskw0 rw 0 bit 1 reserved reserved rw - - 0 bit 0 reserved reserved rw - - 0 - - 1pwd cpu_t/c [1:0]skew control see table 4: 4-steps skew programming table name control function type 0 cpu_t2/c2 skew control - - - - - - byte 18 pin # see table 4: 4-steps skew programming table i 2 c table: group skew control register bit 7 reserved reserved rw - - 1 bit 6 reserved reserved rw - - 0 bit 5 reserved reserved rw - - 0 bit 4 reserved reserved rw - - 0 bit 3 3v66skw3 rw 0 bit 2 3v66skw2 rw 1 bit 1 3v66skw1 rw 0 bit 0 3v66skw0 rw 0 i 2 c table: group skew control register bit 7 pciskw3 rw 1 bit 6 pciskw2 rw 0 bit 5 pciskw1 rw 0 bit 4 pciskw0 rw 0 bit 3 reserved reserved rw - - 1 bit 2 reserved reserved rw - - 0 bit 1 reserved reserved rw - - 0 bit 0 reserved reserved rw - - 0 - - name - - - - - - - - - byte 19 pin # 1 name pwd control function type 0 - 3v66 [3:0] skew control 16-steps skew control. this byte will advance or delay the skew by 100ps per step - - - pwd pci skew control 16-steps skew control. this byte will advance or delay the skew by 100ps per step - control function type 0 1 byte 20 pin #
16 integrated circuit systems, inc. ICS950223 0496c?05/06/05 i 2 c table: slew rate control register pin # name control function type 0 1 pwd bit 7 pcislw1 rw - - 1 bit 6 pcislw0 rw - - 0 bit 5 pcislw1 rw - - 1 bit 4 pcislw0 rw - - 0 bit 3 3v66slw1 rw - - 1 bit 2 3v66slw1 rw - - 0 bit 1 3v66slw1 rw - - 1 bit 0 3v66slw0 rw - - 0 i 2 c table: slew rate control register bit 7 refslw1 rw - - 1 bit 6 refslw0 rw - - 0 bit 5 pcislw1 rw - - 1 bit 4 pcislw0 rw - - 0 bit 3 pcislw1 rw - - 1 bit 2 pcislw0 rw - - 0 bit 1 pcislw1 rw - - 1 bit 0 pcislw0 rw - - 0 i 2 c table: slew rate control register bit 7 reserved reserved rw - - 1 bit 6 reserved reserved rw - - 0 bit 5 reserved reserved rw - - 1 bit 4 reserved reserved rw - - 0 bit 3 48slw1 rw - - 1 bit 2 48slw0 rw - - 0 bit 1 24_48slw1 rw - - 1 bit 0 24_48slw0 rw - - 0 i 2 c table: slew rate control register bit 7 reserved reserved rw - - 0 bit 6 reserved reserved rw - - 0 bit 5 reserved reserved rw - - 0 bit 4 reserved reserved rw - - 0 bit 3 reserved reserved rw - - 0 bit 2 reserved reserved rw - - 0 bit 1 reserved reserved rw - - 1 bit 0 reserved reserved rw - - 0 3v66[3:2] slew rate control - - - - pci [9:7] slew rate control - - - - pciclk_2 slew rate control - byte 24 pin # - pciclk [1:0] slew rate control - ref slew rate control - - - - byte 21 - - - 3v66 [1:0] slew rate control - 0 control function 1 pwd - pci [6:5] slew rate control - byte 22 pin # name type pci [4:3] slew rate control - byte 23 pin # name control function type 0 1 pwd - 48 slew rate control - - 24_48 slew rate control - 1pwd - - name control function type 0 - - - -
17 integrated circuit systems, inc. ICS950223 0496c?05/06/05 i 2 c table: slew rate control register bit 7 reserved reserved rw - - 0 bit 6 reserved reserved rw - - 0 bit 5 reserved reserved rw - - 0 bit 4 reserved reserved rw - - 0 bit 3 reserved reserved rw - - 0 bit 2 reserved reserved rw - - 0 bit 1 reserved reserved rw - - 0 bit 0 - transfer mode control transfer no transfer 0 - - - - byte 25 pin # - - 1pwd - - name control function type 0
18 integrated circuit systems, inc. ICS950223 0496c?05/06/05 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . . . . . . 0c to +70c case temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operation al sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect p roduct reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd + 0.3 v input low voltage v il v ss - 0.3 0.8 v input high current i ih v in = v dd 5ma input low current i il1 v in = 0 v; inputs with no pull-up resistors -5 ma input low current i il2 v in = 0 v; inputs with pull-up resistors -200 ma operating supply current i dd(op) c l = 0 pf; select @ 100mhz 217 260 ma power down supply current i ddpd c l = 0 pf; with input address to vdd or gnd 31 40 ma input frequency f i v dd = 3.3 v; 11 14.31818 16 mhz c in logic inputs 5 pf c inx x1 & x2 pins 27 45 pf clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 1 1.8 ms skew 1 t cpu-pci v t = 1.5 v 1.5 2.5 3.5 ns 1 guaranteed by design, not 100% tested in production. input capacitance 1
19 integrated circuit systems, inc. ICS950223 0496c?05/06/05 electrical characteristics - cpuclkt/c t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units current source output impedance zo 1 v o = v x 3000 ? volta g e hi g hvhi g h 660 718 850 volta g e low vlow -150 17 150 max volta g e vovs 730 1150 min volta g e vuds -450 -7 crossing voltage (abs) vcross(abs) 250 340 550 mv crossing voltage (var) d-vcross variation of crossing over all ed g es 15 140 mv rise time t r v ol = 0.175v, v oh = 0.525v 175 324 700 ps fall time t f v oh = 0.525v v ol = 0.175v 175 453 700 ps duty cycle d t3 measurement from differential wavefrom 45 50.3 55 % skew t sk3 v t = 50% 58 100 ps jitter, cycle to cycle t jcyc-cyc 1 v t = 50% 56 150 ps 1 guaranteed b y desi g n, not 100% tested in production. statistical measurement on sin g le mv measurement on single ended si g nal usin g mv electrical characteristics - pciclk t a = 0 - 70c; v dd = 3.3 v,+/-5%; c l = 30 pf parameter symbol conditions min typ max units output frequency f o1 33.33 mhz output high voltage v oh 1 i oh = -18ma 2.1 v output low voltage v ol 1 i ol = 9.4ma 0.4 v output high current i oh 1 v oh = 2.0 v -22 ma output low current i ol 1 v ol = 0.8 v 16 57 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 1.7 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 1.6 2 ns duty cycle d t1 1 v t = 1.5 v 45 51.5 55 % skew t sk1 1 v t = 1.5 v 61 500 ps jitter,cycle to cyc t jcyc-cyc 1 v t = 1.5 v 114 500 ps 1 guaranteed by design, not 100% tested in production.
20 integrated circuit systems, inc. ICS950223 0496c?05/06/05 electrical characteristics - 3v66 t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output frequency f o1 66.6 mhz output impedance r dsp1 1 v o = v dd *(0.5) 12 33 55 ? output high voltage v oh 1 i oh = -1 ma 2.4 v output low voltage v ol 1 i ol = 1 ma 0.55 v output high current i oh 1 v oh@min = 1.0 v, v oh@max = 3.135 v -33 -33 ma output low current i ol 1 v ol @min = 1.95 v, v ol @max = 0.4 v 30 38 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.5 1.9 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.5 1.7 2 ns duty cycle d t1 1 v t = 1.5 v 45 51.5 55 % skew t sk1 1 v t = 1.5 v 71 250 ps jitter t additive 1 v t = 1.5 v 105 250 ps electrical characteristics - vch, 48mhz dot, 48mhz, usb t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output frequency f o1 48 mhz output impedance r dsp1 1 v o = v dd *(0.5) 20 60 ? output high voltage v oh 1 i oh = -1 ma 2.4 v output low voltage v ol 1 i ol = 1 ma 0.4 v v oh@min = 1.0 v, -29 output high current i oh 1 v oh@max = 3.135 v -23 ma output low current i ol 1 v ol @min = 1.95 v, v ol @max = 0.4 v 29 27 ma 48mhz rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.5 1 2 ns 48mhz fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.5 1 2 ns 24mhz rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 1 1.3 2 ns 24mhz fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 1 1.4 2 ns 48 mhz duty cycle d t1 1 v t = 1.5 v 45 52.3 55 % 24mhz duty cycle d t1 1 v t = 1.5 v 45 50.2 55 % 48 mhz jitter t j c y c-c y c 1 v t = 1.5 v 139 350 ps 24mhz jitter t jcyc-cyc 1 v t = 1.5 v 123 350 ps 1 guaranteed b y desi g n, not 100% tested in production.
21 integrated circuit systems, inc. ICS950223 0496c?05/06/05 electrical characteristics - ref t a = 0 - 70c; v dd = 3.3 v , +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output frequency f o1 14.3 mhz output impedance r dsp1 1 v o = v dd *(0.5) 20 60 ? output high voltage v oh 1 i oh = -12ma 0.4 v output low voltage v ol 1 i ol = 9 ma v output high current i oh 1 v oh = 2.0 v -33 ma output low current i ol 1 v ol = 0.8 v 38 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 1 2.2 4 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 1 2.3 4 ns duty cycle d t1 1 v t = 1.5 v 45 54.1 55 % jitter t jcyc-cyc 1 v t = 1.5 v 129 1000 ps 1 guaranteed b y desi g n, not 100% tested in production.
22 integrated circuit systems, inc. ICS950223 0496c?05/06/05 fig. 1 shared pin operation - input/output pins the i/o pins designated by (input/output) serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm (10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. figure 1 shows a means of implementing this function when a switch or 2 pin header is used. with no jumper is installed the via to vdd clock trace to load series term. res. programming header via to gnd device pad 2k 8.2k pin will be pulled high. with the jumper in place the pin will be pulled low. if programmability is not necessary, than only a single resistor is necessary. the programming resistors should be located close to the series termination resistor to minimize the current loop area. it is more important to locate the series termination resistor close to the driver than the programming resistor.
integrated circuit systems, inc. ICS950223 23 0496c?05/06/05 ICS950223 y flft ordering information example: ics xxxxxx y f lf - t designation for tape and reel packaging annealed lead free (optional) package type f=ssop revision designator (will not correlate with datasheet revision) device type prefix ics = standard device 300 mil ssop package index area index area 12 1 2 n d h x 45 h x 45 e1 e seating plane seating plane a1 a e -c- - c - b .10 (.004) c .10 (.004) c c l min max min max a 2.41 2.80 .095 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n 0 8 0 8 min max min max 48 15.75 16.00 .620 .630 10-0034 variations reference doc.: jedec publication 95, mo-118 300 mil ssop n see variations see variations d mm. d (inch) symbol see variations see variations 0.635 basic 0.025 basic common dimensions in millimeters in inches common dimensions
24 integrated circuit systems, inc. ICS950223 0496c?05/06/05 revision history rev. issue date description page # c 5/6/2005 added lf ordering information 23

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